Enabling Precise Timing Control in SDRs
summary
Architectural recipe for implementing loopback delay estimation on a Zynq SoC with concrete trade offs: integer correlation-based delay estimator moved into FPGA, fractional correction kept in software and later on the ARM, integration via AD9361 and gr-iio and Simulink/HDL-generated IP and GNU Radio. Measured offsets are tenths of microseconds versus theory, fractional estimates cluster at 10/16 or 11/16, and alignment stays stable only for roughly 10–60 seconds, so DPD adaptation must run on that time scale.
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chapters (8)
- 0:00Start
- 3:03Digital Pre-Distortion Algorithm
- 5:21The Architecture of the Rf
- 7:18The Design Flow
- 9:21Hdl Code
- 12:06Move the Integer Delay Estimation from Host Pc to the Fpga
- 13:03Fractional Delay Correction
- 14:47Fractional Loopback Delay
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