FPGA Partial Reconfiguration in Software Defined Radio Devices
summary
Demonstrates a working partial reconfiguration flow on a Xilinx-based SDR using RFNoC blocks and Vivado to define a reconfigurable region, generated static and partial bitstreams with UHD image builder, and swapped an FFT for an FIR at runtime while streaming. Tests run on the E310 platform using UHD and the FPGA manager show a gain block toggling from 1 to 2, and measured reconfigure times of 33 ms vs 143 ms, validating correct operation and ~4× faster updates.
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