Fixing the E310 Bottleneck: Implementing a High-Rate Heterogeneous...
summary
E310’s stock transport fails to sustain even a few Msps between FPGA and the ARM while libiio moves multichannel TX/RX at 61.44 Msps on Zynq; the fix replaces the transport with a Xilinx DMA core plus a custom kernel driver that preallocates ~160 MB and uses large DMA buffers with 128 kB transfers in direct register mode. Result: continuous high-rate captures up to a 40 MHz receive path without PS load and burst-to-RAM then write-to-disk that avoids SD card IO limits.
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chapters (8)
- 0:00Start
- 2:19Walkthrough
- 7:41Direct Register Events
- 8:27Theoretical Limit
- 10:47Create the Software
- 13:37Kernel Driver
- 15:51User Space Software
- 19:46Results
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