“Is Parallel Programming still hard? PART 2 of 2”
summary
Survey of hardware and algorithms that explains why cachelines, store buffers and speculative execution force specific code choices and shows concrete tradeoffs: classic Lamport ring vs per-slot atomics and Giacomoni’s variant, a futex-based blocking variant, and a TLS reader-writer that eliminates cross-thread cache misses. Measurements show a simple global-lock gives about 4.3 million handoffs/sec on one socket, per-slot atomics and alignment double throughput, and designs using per-object atomics or queued locks (MCS) reduce bouncing at the cost of complexity and worse writer latency.
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chapters (31)
- 0:00Introduction
- 0:24Hardware loopholes in physics
- 3:37Locality in parallel computing
- 3:59Hardware optimizations overview
- 4:41Big cachelines trade-offs
- 6:45False sharing and alignment
- 7:26Cache prefetching pitfalls
- 8:28Store buffers and memory ordering
- 11:50C++ memory model benefits
- 12:54Big caches and speculative execution
- 14:41Speculative execution downsides
- 15:43Message passing example
- 17:12Hardware visibility advantages
- 17:33Locking basics and issues
- 19:42Cacheline contention in locks
- 20:44Queued locks for scalability
- 21:46Adaptive spin/sleep strategies
- 22:53Reader-writer lock problems
- 24:39Thread-local reader-writer lock
- 26:04Transition to single-producer single-consumer
- 26:56Buffer design goals and trade-offs
- 27:38Single-lock implementation issues
- 29:28Lamport algorithm advantages
- 31:44Giacomoni algorithm improvements
- 33:54False sharing alignment impact
- 35:05Blocking consumer requirements
- 36:10Futex and blocking performance
- 38:01Three-value state algorithm
- 41:23Blocking vs non-blocking trade-offs
- 41:44Talk summary and lessons
- 42:51Q&A session
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