“No Sane Compiler Would Optimize Atomics"
summary
Claim: compilers already optimize atomics and do architecture-specific lowering. Examples: x86 maps atomic loads to MOV and stores to LOCK-prefixed ops while ARM/MIPS use load‑linked/store‑conditional and RISC‑V offers LD/ACQ ST/REL; fences cost roughly 2–200 cycles. Compilers fold paired increments into a single +2, replace load+store with xchg, and can transform RMW+check sequences, but speculative loop hoisting once caused a correctness bug. A backend patch speeds a Hogwild‑style workload but also introduced a regressions later fixed.
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chapters (7)
- 0:00Introduction to atomics
- 1:50Memory model review
- 2:18Hardware and architectures
- 35:27The consume problem
- 35:50Optimizing atomic code
- 44:11Advanced atomic topics
- 53:39Conclusion and takeaways
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