Enable SRIOV on PowerNV Platform
summary
Implements SR-IOV on PowerNV by mapping VFs into Power’s PE abstraction and changing PTM/MDT ordering so VF BDFs are discovered before parent buses; the working patchset merges PF+VFs into one PE to satisfy MDT/MMR alignment and enables SR-IOV on Power7 hardware. Tradeoffs: only 128 PEs available, the TVT enforces a 128 MB minimum DMA chunk and current platforms expose only a few TVT entries (effectively ~4 usable windows), and DMA is limited to 32-bit today — recovery currently resets all VFs in the merged PE.
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chapters (14)
- 0:00Intro
- 0:59Partitionable Endpoint (PE)
- 3:04Resources needed for PE
- 3:42General Concept
- 5:14PE Number and BDF assignment
- 6:19MMIO Resource for PE
- 9:55Limited Number of PES
- 11:17Reorder assignment of PE number
- 13:10MMIO Alignment
- 15:42Option One
- 18:39Current Choice
- 22:00OMA Space Limitation
- 25:3564-bit OMA address is another option
- 26:52Disadvantage of the solution
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