RISC-V Summit Europe 2024
2024-06-24..2024-06-28
Munich, Germany
[RISC-V Summit Europe 2023, RISC-V Summit Europe 2024, RISC-V Summit Europe 2025, RISC-V Summit Europe 2026, RISC-V Summit Europe 2026 Developer Workshops]
| title | author | length |
|---|---|---|
| Boosting AI on Semidynamics RISC-V Cores with Custom Tensor Instructions | P Marcuello | 11m |
Semidynamics builds an All‑in‑one RISC‑V block combining a 4‑way out‑of‑order core, RVV‑compliant vector unit (up to ~2k/4k‑bit lengths) and a shared‑register… | ||
| Breaking the RISC-V Processor Customization Barrier with Formal Verification | Sven Beyer | 09m |
Automated flow called Questa Processor takes ISA specs and generates an LTE formal model that verifies open-source cores like Rocket and CVA6, finds… | ||
| Enhancements to SiFive’s Essential product line | Pete Lewin | 08m |
Gen 4 updates to SiFive Essentials deliver concrete changes: eight distinct CPUs from 32-bit E2 to 64-bit U7 with configurable pipelines (E2 two/three stage… | ||
| Andes High Value RISC-V Processors and Their Application | Frankwell Lin | 12m |
Andes presents concrete CPU IP updates: an TSMC 7nm test chip and evaluation board built around an AX45MP + NX27 RVV at 2.2 GHz running OpenSUSE, demonstrating… | ||
| Driving SoC Innovation with Synopsys RISC-V Solutions | Rich Collins | 11m |
Synopsys outlines specific RISC-V offerings: an ASIP tool generates SDK and RTL for custom processors and early exploration, Imperas Fast processor models for… | ||
| Introduction of XuanTie RISC-V | James Shi (Qinghao Shi) | 13m |
Alibaba XuanTie reports shipped CPU volume grows from 3 billion (2020) to mass production of 4 billion (2023) with 300+ licensees and 800+ IP blocks. Product… | ||
| Accelerate RISC-V DSA design with Virtual Board Builder | Hualin Wu | 14m |
A browser GUI builds a virtual SoC by drag-and-drop and configures an ANDES D45 model, then imports a speech‑recognition network, generates C/weights, and runs… | ||
| AI custom Software/Hardware Interface improving performance 5-10x | Keith Graham | 10m |
Customizing a RISC‑V core via Codasip Studio’s Codasip Fusion adds bounded micro‑accelerators (about 3,000 lines of RTL) to speed a sensor + MCU anomaly… | ||
| ESWIN EIC7700X/7702X, Pioneer of RISC-V Computing Solution | Bo Wang | 06m |
ESWIN launches the EIC7700X and EIC7702X 77 series SoCs with 64-bit RISC-V CPUs (SiFive P550-class) plus a self-developed NPU that claims full‑stack… | ||
| Exploring RISC-V architectures with VPSim, a virtual prototyping environment | Lilia Zaourar | 09m |
VPSim is a CEA List virtual-prototyping environment that claims a practical accuracy vs. speed compromise and now ships open source. It assembles Arm and… | ||
| Heterogeneous Multicore Debugging of RISC-V Cores in Complex Chips | M. Schleinkofer | 11m |
Shows a working Lauterbach setup that controls RISC-V and Cortex cores through a single debug path using the RISC-V debug module + DTM over JTAG or an on‑chip… | ||
| UnityChip Verification: Open-Source RISC-V Verification at BOSC | Shan Liu | 12m |
Verification cost dominates chip schedules: only 24% of ASICs hit first silicon in 2022 and projects spend 50–60% of time on verification, with logical… | ||
| KVM device assignment for virtual machines using the RISC-V IOMMU | Andrew Jones | 16m |
QEMU RISC-V board boots Linux with the RISC-V IOMMU and AIA, KVM and vfio bind two e1000e network adapters into separate guests and show full DMA translation… | ||
| Introducing Sonata — the new open source platform for CHERIoT development | Greg Chadwick | 12m |
Sonata is an open source FPGA development platform that ships a CHERIoT-enabled Ibex core with I2C, SPI, GPIO, PWM, UART and DMA on an Artix-7 FPGA board… | ||
| The NOEL Processor Line | Jan Andersson Nerén | 13m |
NOEL-V is a configurable RV32/RV64 core that implements a super scalar dual-issue in-order pipeline, many RISC‑V extensions (including recent CFI), and strong… | ||
| Hackathon Presentations | Jan-Eric Schärfrich | 46m |
A 25‑student, 4.5‑hour hackathon uses KIP/CODAL, the SDK and Renaissance hardware to speed up a neural‑net inference loop; teams add multiply and MAC… | ||
| The European Accelerator (EPAC) demonstrator with 3 RISC-V based accelerators | F. Mantovanni | 11m |
A taped-out RISC-V chip includes three accelerators (VTI scalar core + wide VPU, VRP, SDX) and boots standard Ubuntu Linux from a companion FPGA that provides… | ||
| RISC-V Instruction Set Explorer (RISE) | Lennart M. Reimann | 10m |
University Demo Day demo of RISC-V Instruction Set Explorer (RISE) shows an in-house simulator that profiles binaries for basic block execution counts… | ||
| Scale4Edge RISC-V Ecosystem | Andreas Mauderer | 11m |
Customized RISC-V chip integrates processor core (tgcc from minus) with CDSL-defined custom instructions—signed saturation, packed dot 8‑bit and zero‑overhead… | ||
| End-to-end flow to automatically generate and integrate RISC-V ISA extensions | Mürmann | 09m |
An end-to-end flow takes a CDSL high-level description and uses HLS → RTL to generate an ISA extension RTL, wraps it with a lightweight uis6 interface and… | ||
| TETRISC SoC, an fault-tolerant and adaptive quad-core system | Junchao Chen | 11m |
A quad-core RISC-V SoC is a fault-tolerant, self-adaptive system taped out in 130 nm that converts an ETH Zurich single‑core design into four cores and adds an… | ||
| RISC-V enabled, low-power CNN classification in Edge devices | Per Andersson | 11m |
A pulse-coherent radar produces streaming matrices that feed two small CNNs (distance and phase/velocity) running on a programmable near-memory computing… | ||
| Simulate, trace, and evaluate a RISC-V system leveraging very long vectors | Pablo Vizcaino | 11m |
A QEMU-based RAV tracing plugin runs RISCV vector binaries on a laptop and produces instruction counts, per-phase scalar/vector breakdowns, and time-series of… | ||
| The role of an Open Computing Architecture in EU Digital sovereignty | Luis Busquets | 16m |
EU policy pushes concrete targets — >10,000 Edge nodes and >75% of companies on cloud by 2030 — and backs hardware with funds: €1.2B project, NextGenerationEU… | ||
| CHERI in out-of-order microarchitectures | Franz Fuchs | 10m |
An open-source CHERI RISC-V stack is running a full CHERI-BSD OS on a Stratix 10 superscalar out-of-order core called CHERI-tuber, using a ported Clang/LLVM… | ||
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