~/talk

The NOEL Processor Line

Talkat RISC-V Summit Europe 2024 · 2024-06-24..06-28· [embedded-and-hardware]
links:none on file
slides:none on file

NOEL-V is a configurable RV32/RV64 core that implements a super scalar dual-issue in-order pipeline, many RISC‑V extensions (including recent CFI), and strong ECC'd DDR2/3/4 controllers used in space‑grade octa‑core designs on radiation‑hardened ASIC tech. It offers L2 variants, stripe memory to boost bandwidth and a hardware-isolated multicore mode plus time‑slotted external DRAM for deterministic latency. NOEL3 is an RV32 barrel core (3–7 stages) for resource‑constrained and many‑core use, RTL exists and first release targets Q1 2025; most IP is open source under a copyleft license.

AI-written summary · about

  1. 0:00Introduction
  2. 0:24NOEL 5 processor overview
  3. 4:18Multi-core system design
  4. 7:19NOEL 6 barrel processor
  5. 9:02Software ecosystem
  6. 10:29Availability and licensing
  7. 10:51Q&A radiation hardening
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