PDL: A High-Level Hardware Design Language for Pipelined Processors
summary
PDL is a domain-specific language that compiles high-level, one-instruction-at-a-time semantics into pipelined hardware by emitting RTL and checking timing-safety: it exposes primitives like speculative call and verify, and a hazard lock API with reservation/block/release plus checkpoint/rollback. The authors reimplement a Chisel five-stage Sodor core, retarget branch predictors and added multiply/divide pipeline modules, run SPEC workloads and report matching CPI with modest area overhead from a prototype compiler, with code on GitHub.
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chapters (7)
- 0:00Pipeline design challenges
- 1:36Handling hazards and stalls
- 3:30Introducing PDL
- 5:31PDL mechanics and features
- 9:30Managing data hazards
- 13:35Evaluation and results
- 15:56Q&A session
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