Fully Verified Open Silicon

on YouTube ↗32m

" summary

OpenTitan presents a full verification pipeline: block and chip-level simulation, FPGA bring-up and imminent tape-out, using commercial EDA (Synopsys, Cadence) and supporting open tools (Fator, varable). The Ibex core uses epmp with 16 regions and new bits: machine-mode lockdown, mwp and a rule lock bypass; verification moves from 66% PMP coverage to 86% with static tests, 95% with constrained random tests, and uses directed tests to hit remaining edge cases (4‑byte regions, per-entry execution, executable-before-and-after MML).

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" chapters (10)

1. 0:00Introduction
2. 1:43Open silicon challenges
3. 3:53OpenTitan progress
4. 9:53OpenTitan verification
5. 13:49Ibex CPU verification
6. 23:56Memory protection testing
7. 24:18Clock domain crossing
8. 26:30Open silicon virtues
9. 28:19OpenTitan next steps
10. 31:34Q&A

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