Multi-Path Transport for RDMA in Datacenters
summary
MP-RDMA presents a concrete design and FPGA prototype that adds only 66B per connection and achieves line-rate sending/receiving with sub-microsecond latency. It uses multi-path ACK-clocking (one congestion window across paths) to steer load without per-path NIC state, an out-of-order-aware path selection with a tiny bitmap and tunable delta to suppress reordering, and a synchronize mechanism to preserve message ordering. Prototype results show up to 45–47% higher utilization and 2×–4× throughput under 0.5%–10% link loss.
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chapters (15)
- 0:00Intro
- 0:26Remote Direct Memory Access
- 1:49Uniqueness of RDMA Environment
- 3:31Challenge #1
- 4:42Multi-Path ACK Clocking
- 7:08Fluid Model
- 7:39Challenge #2
- 9:10Out-of-order Aware Path Selection
- 11:16Experiment Results Adjust A can control out-of-order degree
- 12:08Challenge #3
- 13:47Synchronise Mechanism
- 15:15Implementation
- 15:49Performance Send and receive at line rates
- 16:33Key Results
- 17:00Summary
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