PIMLex: A High-Performance Learned Index with Processing-in-Memory
summary
PIMLex uses a decoupled two-layer structure (small PIM-based search layer of anchor keys plus large DRAM data layer) and PIM-friendly choices: a lookup-table model to avoid floating-point emulation on UPMEM and a hotness-aware replication scheme that spawns extra replicas for hotspots. Implemented on UPMEM (8 GB per device), it reports 36.5× throughput over a naïve PIM learned-index baseline and 2.2× over DRAM ALEX, with insert costs limited by DRAM-side writes.
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chapters (10)
- 0:00PIMLex and learned indexes
- 2:50Learned indexes on PIM challenges
- 4:39PIMLex design overview
- 7:27PIM-friendly model structure
- 9:38Lookup table for floating-point ops
- 11:06Hardware replication for load balancing
- 13:14Evaluation setup and baselines
- 14:41Performance results
- 15:45Large dataset scalability
- 16:08Conclusion and future work
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