ArchTM: Architecture-Aware, High Performance Transaction for Persistent Memory
summary
A transaction system tuned to Intel DCPMM hardware, ArchTM uses a copy-on-write variant with a scalable DRAM lookup table to avoid metadata writes, an annotation scheme (transaction IDs in translation state and object headers) to recover the latest committed copy, and a locality-aware allocator with a single free list plus background defragmentation to force sequential, coalesced 256-byte PM writes. Evaluation on real PM (DCPMM) shows microbenchmarks and PMKV workloads with up to 58x speedup versus competitors (and 5x, 3x, 7x against others).
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chapters (14)
- 0:00Intro
- 0:34Persistent Memory (PM) Has Arrived
- 0:54PM Architecture & Performance Characterization
- 2:50Transactions on Persistent Memory
- 3:21Issues of Existing PM Transactions
- 4:22Issues of Memory Allocation for PM Transactions
- 5:48Design Goals of ArchTM
- 6:41Avoid Small Writes on PM
- 8:18Encourage Coalescable Writes on PM
- 11:46Recovery Management
- 12:34Other Optimization Techniques
- 12:50Evaluation Setup
- 13:12Evaluation: TPC-C & TATP
- 13:30Conclusion
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