Transactional memory
summary
Overview of transactional memory, showing concrete mechanisms and limits: hardware uses cache coherence with extra bits to implement Intel TSX via _XBEGIN/_XABORT, aborting on cache overflow, page faults or interrupts; software uses retry/orElse for conditional waits and composition; practical pattern is hybrid lock elision (speculative transaction then fallback to locks) to accelerate legacy code; a novel technique called lock teleportation moves locks inside a transaction to traverse lists faster. Notes which failures are fatal, when to retry, and that small transactions perform best.
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chapters (25)
- 0:00Start
- 2:29Shared Memory Multiprocessors
- 3:46Free Ride of Software
- 5:54Amdahl's Law
- 8:23The Meaning of Amdahl's Law
- 15:04Advantage of Coarse Brain Locks
- 17:48Locking Relies on Conventions
- 18:54Comment from the Linux Kernel
- 26:22Monitor Weight and Signal
- 26:55The Monitor Weight and Signal Problem
- 28:47The Transactional Manifesto
- 29:14Atomic Transactions
- 34:04Trivial Examples of Atomic Blocks
- 38:16Problems with False Conflicts
- 39:59Conditional Weighting
- 40:51Dangers and Pitfalls with Monitor Weights
- 42:08How To Implement Atomic Transactions inside Inside Programming Languages
- 42:51Hardware Transactional Memory
- 44:02Insight into the Hardware Transactional Memory
- 44:35Standard Cash Coherence
- 53:01Locked Teleportation
- 57:57Memory Management
- 59:27Effect on Energy on Architecture
- 1:00:50Data Structures
- 1:01:40Hype Curve
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01h 01mUnderstanding Hardware Transactional Memory
01h 00mWhat did C++ do for Transactional Memory?
01h 03m“Transactional Memory in Practice"
01h 33mWhy You Should Use Software Transactional Memory
18mThe Semantics of Transactions and Weak Memory in x86, Power, ARM, and C++
15mHTMFS: Strong Consistency Comes for Free with Hardware Transactional Memory...
30mImplementing and Verifying Release-Acquire Transactional Memory in C11
14mArchTM: Architecture-Aware, High Performance Transaction for Persistent Memory
