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Transactional memory

Talkat Hydra 2020 · 2020-07-06..07-09· [concurrency, software-architecture]
slides:none on file

Overview of transactional memory, showing concrete mechanisms and limits: hardware uses cache coherence with extra bits to implement Intel TSX via _XBEGIN/_XABORT, aborting on cache overflow, page faults or interrupts; software uses retry/orElse for conditional waits and composition; practical pattern is hybrid lock elision (speculative transaction then fallback to locks) to accelerate legacy code; a novel technique called lock teleportation moves locks inside a transaction to traverse lists faster. Notes which failures are fatal, when to retry, and that small transactions perform best.

AI-written summary · about

  1. 0:00Start
  2. 2:29Shared Memory Multiprocessors
  3. 3:46Free Ride of Software
  4. 5:54Amdahl's Law
  5. 8:23The Meaning of Amdahl's Law
  6. 15:04Advantage of Coarse Brain Locks
  7. 17:48Locking Relies on Conventions
  8. 18:54Comment from the Linux Kernel
  9. 26:22Monitor Weight and Signal
  10. 26:55The Monitor Weight and Signal Problem
  11. 28:47The Transactional Manifesto
  12. 29:14Atomic Transactions
  13. 34:04Trivial Examples of Atomic Blocks
  14. 38:16Problems with False Conflicts
  15. 39:59Conditional Weighting
  16. 40:51Dangers and Pitfalls with Monitor Weights
  17. 42:08How To Implement Atomic Transactions inside Inside Programming Languages
  18. 42:51Hardware Transactional Memory
  19. 44:02Insight into the Hardware Transactional Memory
  20. 44:35Standard Cash Coherence
  21. 53:01Locked Teleportation
  22. 57:57Memory Management
  23. 59:27Effect on Energy on Architecture
  24. 1:00:50Data Structures
  25. 1:01:40Hype Curve
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