Abusing Your Memory Model for Fun and Profit
summary
Four practical tricks that shave real latency: a transformation makes any open‑address hash table wait‑free for writers and statistically wait‑free readers on x86‑TSO by using a global version counter and in‑place key/value ordering with near 0 cost; epoch reclamation that scales to millions of events by bounding epochs to three values and using per‑thread two refcounts to avoid frequent fences; a single‑writer event count using xadd and futexes that is 8 cycles no atomic on the fast path (vs ~24 cycles); and an async reverse‑barrier implemented with eBPF perf watermarks to make kernel barriers cheap and nonblocking.
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chapters (10)
- 0:00Introduction to memory models
- 2:43Background on cache coherency
- 7:41TSO and memory reordering
- 10:16Fast bounded concurrency hash table
- 17:25Epoch reclamation technique
- 26:44Event counts for lock-free waiting
- 31:46Single-writer event count optimization
- 42:30Reverse barriers for visibility
- 51:05Takeaways and toolkit summary
- 53:37Q&A session
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