Storage and Emerging Memory Architectures
summary
Session contains concrete designs and measured gains: an adaptive switch threshold wear‑leveling scheme uses linear→exponential thresholds in an SSD simulator to cut background GC and boost IO responsiveness, reporting a 27.6% IO improvement in later life while extending erase lifetime; a Horae NDP scheduler prioritizes critical stages across function units and yields ~11% average latency improvement on hybrid host+NDP workloads; a hybrid RRAM/SRAM IMC pairs a 64×64 1T1R RRAM macro with SRAM compensation to recover up to 29.9% accuracy loss from RRAM non‑idealities and shows up to 21.9% post‑mapping accuracy gain; additional WIP items include in‑pixel multi‑level ReRAM inference and a 21‑cycle carry‑free near‑memory adder.
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