Hardware Support for AI
summary
Five short papers report concrete wins: a reservoir computing representation called DPLR dot-product features runs on Zynq-7000 with Vivado HLS and cuts FPGA logic to about one quarter of OMS while matching or exceeding accuracy and trimming power/memory by orders of magnitude. A differentiable bit‑sharing ensemble yields 22× model-size reduction with only ~36% longer trimming time and preserved accuracy. Bit‑slicing for FHE (SEAL, GPU-backed) gives a 37× FHE speedup after quantization (≤2% accuracy loss). Object detection pipeline shows an 8× detector speedup with negligible accuracy drop. MLP‑Mixer partitioning gives up to 3.1× runtime gains depending on heterogeneity.
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