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John Wickerson

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titleconferencedate
Uniformity Analysis in the WebGPU Shading LanguagePLDI 20262026-06-15
Provides a rigorous operational semantics for TinyWGSL that defines barrier divergence, formalizes the WGSL uniformity rules, and proves soundness sketches…
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QuteFuzz: Fuzzing quantum compilers using randomly generated circuits with control(…)PLanQC 20252025-01-25
QuteFuzz generates fully random quantum programs with nested subroutines and control flow, runs them through Qiskit, Pytket and Cirq stacks, and does…
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Mix Testing: Specifying and Testing ABI Compatibility of C/C++ Atomics ImplementationsOOPSLA 20242024-10-20
Tooling and results: a new testing technique compiles individual C/C++ atomic operations with multiple mappings, links the permutations, and checks whether…
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Hyperblock Scheduling for Verified High-Level SynthesisPLDI 20242024-06-24
A verified HLS backend implements a hyperblock scheduler with operation chaining and a system-of-difference-constraints LP scheduler, emits schedules checked…
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WelcomeThe Future of Weak Memory 20242024-01-15
Program opens by defining weak versus strong memory and lists concrete agenda items: empirical validation of memory persistency models, tooling for checking…
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Extraordinary Meeting: The Publicity Chairs Reflect on the Peer-Review ProcessPOPL 20242024-01-14
A reflective, often comic diagnosis of peer review that names concrete pain points and behavior not just ideals It highlights workload pressures with numbers…
Talk
Taking Back Control in an Intermediate Representation for GPU ComputingPOPL 20232023-01-15
Formal modeling of SPIR-V control flow encodes the rules in an Alloy model, replaces brittle dominance rules with structural dominance that counts control…
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Specifying and Testing GPU Workgroup Progress ModelsOOPSLA 20212021-10-17
A toolbox formalizes a tiny concurrent language, implements executable semantics in the CDP model checker, synthesizes 483 litmus tests, compiles them to…
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The Semantics of Shared Memory in Intel CPU/FPGA SystemsOOPSLA 20212021-10-17
Defines precise weak‑memory behaviors for Intel Xeon + Arria FPGA systems, encoding them as an operational model in CBMC and an axiomatic model in Alloy and…
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Formal Verification of High-Level SynthesisOOPSLA 20212021-10-17
Presents a mechanically verified HLS tool called Vericert that extends CompCert and is proved correct in Coq, translating CompCert 3AC into an HTL FSM and then…
Talk
Ask Me Anything with Peter O'HearnPLDI 20202020-06-15
Answers claim a shift from heavy upfront specs to a pay-as-you-go model where small specs give incremental value, and point to concrete tools: Infer team work…
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The Semantics of Transactions and Weak Memory in x86, Power, ARM, and C++USENIX ATC '192019-07-10
Extends existing axiomatic models for x86, Power, ARMv8 and C++ with concrete TM rules and proves sanity properties (transactions never enable previously…
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