RISC-V Forum: Developer Tools and Tool Chains 2021
2021-06-02
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| title | author | length |
|---|---|---|
| Welcome to the RISC-V Developer Tools & Tool Chains Forum | Kim McMahon | 04m |
Opens the forum agenda and orients attendees to community resources for the open ISA offering an explicit call to contribute code reviews, compliance tests and… | ||
| RISC-V Tools & Runtime HSC Overview | Christoph Müllner, Philipp Tomsich | 16m |
Committee forms nine to ten months ago and coordinates upstream work so new ISA extensions ship with compiler and runtime support; toolchain changes target… | ||
| Java on RISC-V: OpenJDK Porting Work Update | Sanhong Li, Kevin Kuai | 26m |
OpenJDK runs on RISC-V via a zero back end interpreter and Huawei’s upstream port that adds template interpreter plus C1/C2 is merged into Alibaba Dragonwell… | ||
| Analysis for Code Size Opportunities in RISC V | Ibrahim Abu Kharmeh | 20m |
Describes a practical evaluation of the Zce extension using an objdump-parsed Python script that builds instruction records, simulates replacing sequences… | ||
| Programmer Productivity and Performance on Embedded RISC-V CPUs | Nick Brown | 09m |
ePython implements a 24KB interpreter for tiny RISC‑V embedded cores and uses the Olympus compiler with a novel dynamic-loading technique to run effectively… | ||
| CFU Playground: Model-specific Acceleration on FPGAs | Timothy Callahan, Alan V. Green | 30m |
CFU Playground is an open source framework that lets engineers add a custom function unit to a VexRiscv soft RISC‑V core on FPGA and specialize TensorFlow Lite… | ||
| Linker Relaxation in LLD | Chih-Mao Chen | 22m |
LLD gains a RISC-V linker relaxation pass that rewrites conservative compiler sequences into smaller ones (AUIPC+JALR → JAL, JAL → compressed jumps) and… | ||
| Exploring Static Code Generation and SIMD-Acceleration for Machine Learning on RISC-V | Rafael Stahl | 17m |
Static code generators based on TensorFlow Lite for Microcontrollers and TVM emit model-specific C so model loading and interpreter overhead disappear, while… | ||
| Porting and Optimization V8 for RISC-V | Ji Qiu | 08m |
Upstreamed a full V8 port for the RV64G/RISC-V64 ISA and now maintain two CI branches (master and riscv64), with four months of rebasing before landing and… | ||
| Panel: Toolchains & Runtime | P. Tomsich, C. Müllner, K. Cheng, E. Menezes, J. Clarke, J. Leidel | 40m |
Panel reports that RISC-V’s scalable vector v1.0 work-in-progress brings many instructions but real compiler gaps remain: segmented loads/stores are awkward… | ||
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