SMART: A High-Performance Adaptive Radix Tree for Disaggregated Memory
summary
Builds a radix tree tuned for disaggregated memory and actually implements it: internal pointers live in fixed-size slots updated atomically via RDMA compare-and-swap, leaves use fine-grained in-place updates with checksum and log embedding, and cache validation uses a reverse-pointer check. It cuts redundant remote I/Os with read-delegation and write-combining at the compute side. Evaluated on 16 compute + 2 memory nodes with YCSB integer-key workloads on CloudLab, it reports up to 6.1× higher throughput for write-heavy and 2.8× for read-only vs state-of-the-art B+ trees.
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chapters (10)
- 0:00Introduction to Smart
- 0:36Disaggregated memory basics
- 1:18Tree index challenges
- 2:32Analysis of existing designs
- 3:30Key research challenges
- 5:30Smart design components
- 7:32Delegation and combining
- 9:30Cache invalidation
- 10:44Experimental results
- 12:47Conclusion
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