The Big-endian RISC-V Linux Adventure
summary
Prototype implements RISC-V runtime data endianness via MSTATUS MBE bits (bit 37/36), modifies QEMU (about 120 LOC in target/riscv and translation), updates OpenSBI and the Linux tree (roughly 2,033 LOC mainly around probes, BPF JIT and instruction-modifying code), and adds a kvmtool option to run mixed-endian guests. Instruction stream remains little-endian; page tables follow S-mode. FPGA CVA6 port runs integer loads/stores but atomics still fail. ZBB byte-reverse gives up to ~5x speedup for 64-bit swaps.
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chapters (15)
- 0:00Big-endian RISC-V project intro
- 2:12Endianness significance
- 6:13Planning RISC-V big-endian
- 8:49QEMU big-endian RISC-V
- 12:45Software stack for big-endian RISC-V
- 15:39OpenSBI and kernel big-endian
- 19:31Networking and peripheral endianness
- 20:35Debugging kernel instructions
- 24:52Booting big-endian Linux
- 26:17Debugging unaligned memory
- 29:10Future work for big-endian RISC-V
- 31:15Testing on CVA6 and MIPS
- 34:45Upstreaming challenges
- 37:15Project resources
- 39:32Q&A
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