CPU Cache Effects
summary
Benchmarks show concrete numbers: tight loops hit ~12–13 billion ops/s until they outgrow L1 and drop to ~2 billion ops/s once hitting RAM, and L1 hits cost ~4–5 cycles (~2–3 ns). Experiments demonstrate a ~3× speedup for large memset when using non-temporal stores, explain 64-byte cache line effects (stride and alignment matter), expose associativity pitfalls that cause ~10× slowdowns for power‑of‑two strides, and measure memory parallelism at about 13–17 concurrent memory ops; use perf and cachegrind to reproduce.
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chapters (19)
- 0:00CPU cache importance
- 1:02Memory access time
- 3:51Optimizing memory efficiency
- 5:39Measuring memory bandwidth
- 10:23Read vs write bandwidth
- 13:14Non-temporal memory accesses
- 17:35RAM vs CPU cache bandwidth
- 18:39Measuring memory latency
- 23:32Cache lines impact
- 25:37Counting cache lines
- 26:21Memory alignment design
- 32:30Memory level parallelism
- 35:02Memory parallelism in data structures
- 36:26Pointers vs indices
- 39:17Shared caches performance
- 41:05Measuring multi-threaded bandwidth
- 45:43Cache prefetching
- 51:24Cache associativity anomalies
- 1:02:34Further resources
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