Efficient GPU Implementation of Affine Index Permutations on Arrays
summary
Presents GPU kernels that implement BMMC (bit-matrix-multiply-complement) index permutations with performance comparable to as fast as a simple array copy, using tiled shared-memory reads/writes and bitwise linear-algebra on indices. A BPC (bit-permute-complement) kernel uses one kernel for BPC, two for BMMC; BPC runs nearly at a 9.5 ms reference copy, tiled transpose gives >2× speedup over naive, and larger arrays amplify gains. Works for FFT bit-reversal, Palm combinator and sorting-network layouts; requires power-of-two sizes and an offline-known permutation.
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chapters (11)
- 0:00Introduction
- 4:03GPU architecture basics
- 7:16Matrix transposition on GPUs
- 11:57Affine index permutations
- 16:13Bit-permute-complement permutations
- 20:45Implementing the Palm combinator
- 25:29Tiled kernel for BPC
- 28:01Generalizing to BMMC
- 32:00Performance evaluation
- 35:15Summary and limitations
- 36:21Q&A
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