~/talk

The Foundation of C++ Atomics: The Knowledge You Need to Correctly Use C++ Atomics

Talkat CppCon 2021 · on Wednesday, 2021-10-27· at 07:45· Online A, online· [security]
links:none on file
slides:none on file

Covers concrete rules and mechanisms: std::atomic (six memory orderings) and when each actually maps to fences or machine instructions, how a core’s store queue / reorder buffer makes x86’s TSO: store can reorder with later load observable, and why loads can take hundreds of cycles and must search the store buffer for forwarding. Shows performance numbers (pipelines from 16→7 cycles, in-order vs out-of-order 16→12 cycles) and ties C++ memory orders to compiler/hardware behavior.

AI-written summary · about

  1. 0:00Start
  2. 3:42Why Do We Need Atomics
  3. 4:14Difference between Memory Consistent and Cache Coherence
  4. 5:39Can Two Processors Be in the Critical Section
  5. 7:30Why Is It Important To Protect Child Data
  6. 8:10Why Two Threads Can Be at the Critical Section at the Same Time
  7. 11:54Sequential Consistency
  8. 14:40Relaxed Memory Model
  9. 19:54Why To Keep a Buffer inside of a Core
  10. 21:03Pipeline Processor
  11. 23:20Problem of External Fragmentation
  12. 23:53Data Dependencies
  13. 24:56Output Dependencies
  14. 39:59Reorder Buffer
  15. 50:10Dynamic Instruction Scheduling
  16. 59:43Out of Order Machines
  17. 1:01:10Out of Order Execution
  18. 1:03:59Memory Operations
  19. 1:07:07Memo Disambiguation Problem
  20. 1:07:46Memory Examination Problem
  21. 1:11:28How Does the out-of-Order Engine Detect the Dependence of a Load Instruction
  22. 1:12:28How Does the out of Order Engine Treat the Scheduling of a Load Instruction with Regards to Previous Stores
  23. 1:13:14The Aggressive Approach
  24. 1:13:36Intelligent Approach
  25. 1:14:21Data Forwarding between Stores and Loads
  26. 1:24:38Buffer Affects the Visibility of Storage Operations
  27. 1:30:30Exploit Memory Level Parallelism
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