C++20 on Xilinx FPGA with SYCL for Vitis

on YouTube ↗01h 09m

" summary

Claims that a merged Intel oneAPI DPC++ and triSYCL implementation lets C++20/SYCL compile to Xilinx Alveo FPGA bitstreams, producing single-source C++ SYCL kernels that map to FPGA pipelines and custom memories. Shows an open repo, an Alveo-targeting SYCL backend plus an emulator, demonstrates Monte Carlo and pixel effects running on FPGA hardware, achieves megahertz-range kernel frequencies, and reports that generated kernels and dataflow pipelines actually synthesize and run end to end.

AI-written summary · about

" chapters (12)

1. 0:00Modern FPGA challenges
2. 4:09Why hardware acceleration
3. 10:18SYCL and C++20 for FPGA
4. 16:44Hardware-software co-design
5. 24:23SYCL on Xilinx FPGA demo
6. 31:23Kernel execution and memory
7. 38:17Dynamic polymorphism in SYCL
8. 45:06Optimizing memory access
9. 52:01Generic kernel programming
10. 58:26Debugging SYCL apps
11. 1:00:10SYCL and FPGA future
12. 1:02:31Q&A

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