How shit works: the CPU
summary
Generates a 32KB random byte array, then benchmarks iterating and summing positives before and after sorting using JMH and finds the sorted version runs about 10× faster; explanation ties the speedup to predictable branches and the CPU prefetcher. Notes memory latency ~60 ns ≈ 250 cycles, L1 cache hits at ~4–5 cycles, and that caches move data in cache line = 64 bytes chunks. Shows a 4K image transpose where blocking (tiles) improves throughput up to ~2.37× by reducing cache thrash.
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chapters (13)
- 0:00Introduction
- 1:03Performance puzzle
- 3:33CPU complexity
- 7:02CPU architecture
- 10:34Execution units
- 11:18CPU pipelining
- 16:35Pipeline stalls
- 16:56Memory latency
- 19:27CPU cache hierarchy
- 23:20Cache-friendly code
- 28:19Branch prediction
- 31:31Sorted data advantage
- 34:15Q&A
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