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Myoungsoo Jung

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ScalaAFA: Constructing User-Space All-Flash Array Engine with Holistic DesignsUSENIX ATC 20242024-07-10
ScalaAFA is a user-space all‑flash array engine implemented on SPDK and evaluated with FAMU-emulated PCIe5 SSDs that offload replication‑to‑striping conversion…
Talk
CXL-ANNS: Software-Hardware Collaborative Memory Disaggregation and Computation...USENIX ATC '232023-07-10
CXL-ANNS places billion-point graphs and embeddings in a CXL memory pool, adds a local DRAM cache of inner nodes (59% hit rate with 128 GB local memory) and…
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Direct Access, High-Performance Memory Disaggregation with DirectCXLUSENIX ATC '222022-07-11
Built a full CXL v2 prototype—DirectCXL prototype—including a CXL root-port CPU, CXL endpoint memory device, reconfigurable switch and a Linux runtime that…
Talk on
Vigil-KV: Hardware-Software Co-Design to Integrate Strong Latency Determinism...USENIX ATC '222022-07-11
Claims that predictable latency mode (PLM) per NVMe partition and coordinated host scheduling eliminate long-tail reads, implemented by partitioning a 1.92TB…
Talk
Hardware/Software Co-Programmable Framework for Computational SSDs to Accelerate Deep...FAST '222022-02-22
HolisticGNN implements a FPGA-based computational SSD that stores graphs as neighbor-oriented adjacency lists, exposes RPC over PCIe and runs programmable GNN…
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OpenExpress: Fully Hardware Automated Open Research Framework for Future Fast...USENIX ATC '202020-07-15
OpenExpress is an open RTL framework that implements NVMe queue, PRP parsing and MSI handling entirely in logic and runs on an UltraScale FPGA with 4×64 GB…
Talk
Platform-Agnostic Lightweight Deep Learning for Garbage Collection...12th USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage '20)2020-07-13
A platform-agnostic GC scheduler called GC Tutor uses a lightweight DNN classifier to predict the idle time between the last and next I/O request and schedules…
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TensorPRAM: Designing a Scalable Heterogeneous Deep Learning Accelerator12th USENIX Workshop on Hot Topics in Storage and File Systems (HotStorage '20)2020-07-13
Design replaces DRAM with byte-addressable PRAM inside an FPGA-based accelerator so model weights and activations sit on nonvolatile memory and avoid…
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Scalable Parallel Flash Firmware for Many-core ArchitecturesFAST '202020-02-24
DeepFlash claims a concrete result: a manycore SSD firmware that reaches 1M IOPS and about 4.5 GB/s by splitting firmware into modular “stresses” and running a…
Talk on
DC-Store: Eliminating Noisy Neighbor Containers using Deterministic I/O PerformanceFAST '202020-02-24
DC-Store claims deterministic I/O and removes noisy-neighbor effects by physically dividing an SSD into four NVM sets (prototype uses 2 channels per set on a 2…
Talk on
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