Panel Discussion
summary
Panel covers concrete roadmaps and trade-offs: comparisons of surface codes vs LDPC, modular chip linking vs monolithic scaling, and compiler-to-hardware baselines inspired by the Tour de Gros architecture. Targets include a 10^-10 target logical error rate and demonstrations of long-lived logical qubits (million-cycle / hour timescales). Major practical challenges are leakage, crosstalk, decoder latency and FPGA deployment; neutral-atom systems report 3,000-qubit continuous operation and industry plans a small Gross-code demo in 2026.
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chapters (11)
- 0:00Quantum fault tolerance intro
- 1:03Primary challenges
- 15:14Noise and leakage in error correction
- 21:48Scalability and modularity
- 26:30Quantum architectures explored
- 34:08Current limitations
- 38:46Transition to science
- 42:21Beyond qubits
- 44:11Next milestones
- 47:02Evidence to change direction
- 50:59Closing remarks
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