RIVIERAA Programmable RISC V Edge Architecture

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" summary

NXP develops RIVIERA, a RISC-V edge architecture for NFC that moves DSP tasks to a microprocessor plus tightly coupled hardware accelerator using the ISA extension interface. Two variants exist: a conservative MPU for auxiliary DSP and an ambitious design that replaces RX/TX paths. Iterations cut required clock from GHz to ~100 MHz, making integration into existing NFC SoCs feasible. Implementation runs on silicon-level SoC prototypes and FPGA-stimulus tests, decodes frames correctly and tolerates added noise with a remaining performance gap to hand-tuned hardware.

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" chapters (7)

1. 0:00Introduction
2. 1:06NFC background and challenges
3. 4:37Riviera architecture concept
4. 6:45Conservative architecture details
5. 7:08Riviera ambitious architecture
6. 9:43Performance results and feasibility
7. 12:28Conclusion and future outlook

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