Enabling Virtualisation on RISC-V Microcontrollers
summary
Proposal splits machine mode into EM/RM CSR replication so guests run in EM with redirected CSRs while RM holds originals and new controls, and adds a lightweight segmentation-based relocation (single-level) to give memory transparency without full virtual memory. Two protection implementations: a table-backed second PMP/PMR or a compressed radix-trie walker, trading hardware cost and latency against flexibility. Design targets bare-metal/RTOS guests, targets an Ibex (lowRISC) PoC, and notes context-switch, interrupt and cache costs remain to be measured.
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