The two memory models
summary
Clear, actionable comparison of the C++ memory model and CPU memory models with concrete examples: a producer/consumer ready flag example that shows why atomics need release/acquire (or seq_cst) to establish happens‑before, and why relaxed atomics look identical in assembly yet produce UB on relaxed architectures; demonstration uses GCC 15.1 -O3 assembly demo and contrasts x86’s TSO (stores not reordered before loads) with RISC‑V/ARM’s more relaxed rules requiring fences, and shows the exact places the compiler must insert fences.
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chapters (11)
- 0:00C++ memory models intro
- 1:03Why study two models
- 7:18Single-thread ordering
- 18:51Multi-threaded data races
- 23:48Happens-before in C++
- 28:27Atomic operations and orders
- 37:01CPU reordering effects
- 42:56Sequentially vs relaxed CPU
- 49:17Relaxed models like RISC-V
- 55:13Language vs CPU differences
- 56:17Q&A
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