Optimized String Processing in RISC-V: How Toolchain Improvements Can Boost Performance
summary
Toolchain patches use RISC‑V bytewise instructions (orc.b/zbb) and the XTHead test‑not‑byte‑zero variant to implement a fast find-zero sequence that drops a 10‑instruction loop to ~2–3 instructions, exposed via GCC intrinsics and glibc runtime dispatch (IUN/PLT + kernel hwprobe). Microbenchmarks show up to 147% throughput improvement (and similar peaks on another board), but SPEC CPU2017 shows negligible overall change because of limited libc string use and memory‑bandwidth saturation.
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chapters (19)
- 0:00Optimized string processing intro
- 1:24String functions focus
- 3:10RISC-V and bit extensions
- 4:58String function challenges
- 7:22SIMD in RISC-V P extension
- 8:47Lamport string comparison
- 10:11Zero-byte detection in GCC
- 14:36String optimization strategy
- 15:41Pointer alignment in strings
- 19:00Reducing zero-byte instructions
- 20:31GCC optimization integration
- 22:43glibc IFUNC runtime
- 25:35Benchmarking performance
- 26:37Micro-benchmark length
- 30:32Dhrystone benchmark performance
- 31:38SPEC CPU 2017 results
- 33:04Upstream optimization status
- 34:48Optimizations summary
- 35:10Q&A
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