The Secure Design in Zephyr and its Implementation in Synopsys ARC Processor
summary
Describes Zephyr RTOS security features—specifically its memory protection mechanisms and Trusted Execution Environment—and reports on recent Zephyr development progress. Explains how those secure-design components are supported and implemented on Synopsys ARC processor architectures.
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chapters (16)
- 0:00Start
- 3:32Architecture and Key Features
- 3:47What's New
- 5:40Zephyr Development Flow
- 9:57Auditable Code Base
- 11:29User Space in Zephyr
- 12:54User Mode
- 15:24Kernel Objects
- 16:21System Call
- 17:02Memory Map • Correct memory map is the
- 19:05Trusted Execution Environment
- 20:47Zephyr and TEE
- 23:09ARC Support in Zephyr
- 24:09EM Processor Security Features
- 25:04ARC SecureShield Runtime
- 26:07ARC TEE in Zephyr
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