Overcoming Capacitance Constraints in SSD (Work-in-Progress Report)
summary
Proposes a divided-architecture SSD that avoids full capacitor-backed PRP by protecting only 1% of mapping entries and forcing cold mapping pages to land in flash, claiming large capacitance savings. Uses NVMe 64k command queues to batch and aggregate mapping updates, reducing flushes and mapping-write traffic; a prototype extends an SSD emulator and configures a 64 GB device with small protected memory, writing 90 GB into a 30 GB working set. Reports higher IOPS under high locality and that sequential throughput matches the baseline.
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