FPGA-Accelerated Compactions for LSM based Key-Value Store
summary
Offloads LSM compactions to FPGA co‑processors integrated with X-Engine, implementing pipelined decoder–merger–encoder compaction units over PCIe and running up to eight CUs per board. Measures show 2–5× compaction throughput, up to 23% higher database throughput and 31.7% better transactions‑per‑watt versus a tuned CPU baseline, with only ~0.03% of tasks falling back to CPU because of a 6KB value size limit; current bitstream uses roughly half the FPGA resources.
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chapters (11)
- 0:00Start
- 1:41LSM-based Key-Value Store
- 2:49The Performance Fatigue Problem
- 6:56Integrating FPGA as a co-processor
- 12:14Experimental Setup
- 12:30Evaluating the FPGA-based Compaction
- 13:29Compaction Unit Resource Consumption
- 16:27Macro-benchmark
- 17:32Evaluation Takeaways
- 17:58Conclusion
- 19:28The Value of Adding an FPGA
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