Open Loop Testing: The Missing Link for Embedded Testing?
summary
Argues that open loop tests let developers exercise driver code directly instead of expensive system simulations, demonstrating a concrete embeff test box that flashes firmware, invokes driver functions via Robot Framework, and routes all MCU pins through an FPGA to a logic analyzer. Tests measure pulse lengths on an STM32 (7 ms and 600 μs pass; 50 μs reads 52 μs and fails a one percent tolerance), shows hardware PWM fixes timing, and supports fast, automatable driver-level TDD.
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chapters (17)
- 0:00Introduction to embedded testing
- 2:31Foundations of embedded systems
- 6:08Silicon complexity challenges
- 7:11Vendor driver limitations
- 8:39Traditional system testing flaws
- 11:30Closed loop testing explained
- 13:40Open loop testing concept
- 15:48Open loop test structure
- 16:10Pulse generation driver test
- 16:54Live demo setup
- 21:31Automated pulse measurement
- 24:19Testing multiple pulse lengths
- 26:09Debugging timing inaccuracies
- 27:56Hardware-based pulse generation
- 29:33Summary and conclusions
- 30:58Open loop testing benefits
- 31:43Q&A: Device used for pin analysis
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