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A dive into RISC-V

Talkat dotGo 2019 · on Monday, 2019-03-25· [webassembly]
slides:none on file

Overview of what RISC-V actually does and what was built: RISC-V defines an open instruction set with a minimal base plus extensions that vendors can add, which simplifies auditing and lets firmware run from bare metal. The talk shows concrete ecosystem status: open firmware tools exist, Linux runs on RISC-V boards, but Go support is fractured — old Go ports compile but modern compiler changes break builds and tools like tinyGo and Rust bare‑metal work are promising.

AI-written summary · about

  1. 0:00Start
  2. 0:12Introduction to RISC-V
  3. 0:37What is RISC-V?
  4. 3:49VLIN (very long instruction word), LIM (long instruction word), EPIC (explicitly parallel instruction computing): designed to exploit Instruction level parallelisn. executing multiple instructions in parallel. This requires less hardware than CISC or RISC and leaves the complexity for the compiler
  5. 12:30Mirageos Unikernels as firmware
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