The Shape of Things to Come
summary
A Python/C++/Rust DSL (cuTile) plus an MLIR-based array ISA (TileIR) targets portable, tile-level CUDA kernels that shift memory movement and tiling into the compiler. Real results: single implementations drop 10,035 lines to 78, sparse MVM shows ~3× speedup, many kernels sit within 5–10% of state of the art and some H100 cases hit 1.7× cudnn; kernels launch with normal CUDA APIs, support async TMA/DMA, autotune tile sizes, and use an unordered memory model with explicit tokens for safe ordering.
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chapters (27)
- 0:00Keynote introduction
- 0:43Evolve GPU programming model
- 2:49Hardware evolution challenges
- 4:12Three GPU programming tiers
- 5:36PEX abstraction limits
- 7:00Tile programming model intro
- 10:05Tile abstraction goals
- 12:16Compiler-driven solutions shift
- 15:45Coutile Python DSL
- 20:18Tile IR semantics deep dive
- 28:39Memory model unordered ops
- 32:31Autotuning performance hints
- 33:33Future language integrations
- 34:34C++ tile programming native
- 36:43Tile performance improvements
- 40:37Interoperability with code
- 44:30Async communication challenges
- 46:14Math libraries impact
- 47:19Roadmap upcoming features
- 48:22Q&A hardware mapping
- 50:08Q&A async pipelining
- 51:32Q&A tile locality profiling
- 52:57Q&A compiler burden
- 55:01Q&A low-level access
- 56:46Q&A autotuning strategies
- 58:29Q&A token memory model
- 59:32Closing remarks
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