GHC’s RISC-V Native Code Generation Backend

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" summary

GHC gains a RISC-V Native Code Generator that lands in the tree (merged last summer and tracked as GHC 9.12 merge), complements the earlier LLVM backend, and provides static linking via an RTS linker and a working cross-compiler path; current targets are rv64g plus compressed instructions and the backend passes the full compiler test-suite passing minus SIMD. SIMD/vector support is work in progress (vsetvl based reconfigurable vectors discussed), hardware scarcity keeps RISC-V at tier three, and practical CI/debugging tricks and build-farm patches are documented.

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" chapters (7)

1. 0:00RISC-V architecture intro
2. 3:01RISC-V hardware and tools
3. 10:15RISC-V support history in GHC
4. 12:44GHC RISC-V backend status
5. 14:52RISC-V vector registers
6. 22:02Future RISC-V backend tasks
7. 24:10Q&A on vector mapping

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