Matheus Cavalcante
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| title | conference | date |
|---|---|---|
| Ara 2 0 64 bit RISC V Vector Processor in 22nm FD SOI | RISC-V Summit 2019 | 2019-12-09 |
Ara 2.0 is a 64-bit RISC‑V crate‑style vector processor taped out in 22nm FD‑SOI and scaled from 4 to 16 lanes; a 4‑lane chip hits ~1.125 GHz and a 16‑lane… | ||
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