Jevin Saju John
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| title | conference | date |
|---|---|---|
| Demo: STING Design Verification: A Robust Approach for Complex RISC-V CPU and SoC Validation | RISC-V Summit North America 2023 | 2023-11-06 |
STING is a RISC‑V verification suite with a random+directed stimulus engine, a STING Configuration Creator (SEC) that derives DUT/board parameters from a… | ||
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