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Chengzhong Xu

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CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the EdgeUSENIX ATC '252025-07-07
Claims a combined algorithm–hardware co‑design that prunes and customizes LLMs to fit edge memory/energy budgets, implements a 28nm scalable accelerator with a…
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AssyLLM: Efficient Federated Fine-tuning of LLMs via Assembling Pre-trained BlocksUSENIX ATC '252025-07-07
AssyLLM assembles pre-trained transformer blocks from multiple LLMs (LLaMA, OPT, etc.) so clients only run forward passes and upload block indices instead of…
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Expeditious High-Concurrency MicroVM SnapStart in Persistent Memory with an...USENIX ATC 20242024-07-10
PASS is a user-space augmented hypervisor that maps entire MicroVM snapshots into a single-tier Intel PMEM address space and implements zero-copy on-demand…
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