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Chaoliang Zeng

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titleconferencedate
Towards Optimal Rack-scale μs-level CPU Scheduling through In-Network Workload...USENIX ATC '252025-07-07
Pallas partitions rack traffic at the ToR so each shard has homogeneous CPU demand, uses a P4-programmed ToR switch for classification and per-group JSQ-style…
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Accelerating Neural Recommendation Training with Embedding Scheduling21st USENIX Symposium on Networked Systems Design and Implementation (NSDI '24)2024-04-16
A runtime embedding scheduler called Herald decides where embeddings are trained and which to sync, using an adaptive location-aware inputs allocator and an…
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SRNIC: A Scalable Architecture for RDMA NICsNSDI 20232023-04-17
Presents SRNIC, an FPGA prototype RDMA NIC architecture that removes on‑chip structures via protocol header extensions, cache‑free QP scheduling, and…
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Tiara: A Scalable and Efficient Hardware Acceleration Architecture for Stateful Layer-419th USENIX Symposium on Networked Systems Design and Implementation (NSDI '22)2022-04-04
Tiara splits stateful L4 load balancing into memory-heavy real-server selection on FPGAs with HBM and throughput-heavy encapsulation on a programmable switch…
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