Ashish Darbari
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| title | conference | date |
|---|---|---|
| Using Formal to Vaccinate RISC-V Designs Against Catastrophic Bugs | RISC-V Global Forum 2020 | 2020-09-03 |
A push‑button Formalizer app synthesizes formal properties from the RISC‑V ISA, runs with any vendor tool (Cadence/Mentor/Synopsys), and outputs proofs plus an… | ||
| Democratising Formal Verification of RISC V Processors | RISC-V Summit 2019 | 2019-12-09 |
A vendor‑agnostic proof kit compiles a RISC‑V core into SystemVerilog assertions and runs on Jasper Cadence Synopsys and OneSpin, requiring ~15–20 lines of… | ||
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