Reactive design patterns for microservices on multicore
summary
An actor-model runtime called Simplx implements one-thread-per-core event loops (idle ~200–400 ns) and unidirectional lock-free channels to scale throughput with core count while keeping end-to-end latency near microseconds (demo shows ~1 µs monitoring latency). Techniques include direct calls for same-core actors, batched cross-core transfers to replace many cache-coherency syncs (MESI round-trip ~600 cycles), splitting large FIX orders to shrink per-order cache footprint from ~200 bytes to ~32 bytes (≈8k orders/core), and a two-table routing map that cuts directory memory ~40–50%.
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chapters (8)
- 0:00Start
- 2:52Highly Interconnected Workflows
- 3:57Evolution of Multi-Core Architectures
- 6:50Sources of Contention and Coherency
- 14:43Test Challenge
- 16:29Messaging
- 28:33Fixed Protocol
- 32:15Routing Pattern Actor Directory
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