Evaluating Candidate Instructions for Reliable Program Slowdown at the Compiler Level -(…)
summary
Evaluation inserts six x86 candidates (NOP, MOV, PAUSE, push/pop variants, SFENCE, vector push/pop) into machine code at basic‑block granularity using compilation replay and Intel VTune hardware‑counter feedback to reach a 100% target slowdown on an Intel Core i5-10600. NOP and MOV achieve near‑target, well‑distributed slowdown and preserve sampling profiles; PAUSE explodes overhead (~11,000%), push/pop ≈200%, SFENCE/long sequences ≈400%, so they overshoot. Methodology also uncovers profiler blind spots: Async/JFR detect forced delays, YourKit/JProfiler can miss them.
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chapters (13)
- 0:00Reliable program slowdown intro
- 1:23Use cases and requirements
- 3:30Methodology and setup
- 7:29Slowdown accuracy and overhead
- 9:13Slowdown distribution across blocks
- 10:18Impact on program behavior
- 11:21Profiler evaluation application
- 12:46Conclusion and viable instructions
- 13:06Q&A: Programmer-specified slowdown
- 14:52Q&A: CPU architecture sensitivity
- 15:35Q&A: Variable block execution time
- 17:23Q&A: Manual timing surprises
- 18:28Q&A: Multi-core slowdown generalization
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