RISC-V Forum: Embedded Technologies 2021
2021-07-21
-- online --
| title | author | length |
|---|---|---|
| RISC-V Welcome | Kim McMahon | 02m |
Third RISC-V Forum: Embedded Technologies opens with sponsor notes: Andy’s Technology showcases a 64-bit RISC-V vector core NX27V upgraded to RVV 0.10 claiming… | ||
| Build RISCV based IOT Systems using Yocto Project | Khem Raj | 19m |
Builds RISC‑V Linux images and SDKs using Yocto Project for QEMU and boards Freedom U540 and BeagleV (beta), with rv64gc and rv32gc support and musl for 32‑bit… | ||
| Automotive Linux for RISC-V | Itai Yarom | 19m |
Automotive Linux for RISC-V - Itai Yarom, Wave Computing
ELISA (Enabling Linux in Safety Applications - https://elisa.tech) is an organization that includes… | ||
| Enabling Crypto Agility by Immunizing Processors Against the Exploitation of Software Bugs | Steven Milburn | 13m |
Moving cryptography back into software buys crypto agility but exposes keys and algorithms to software bugs, side channels and update-supply-chain attacks… | ||
| RISC-V Grows Up and Goes Big! | John Min | 14m |
Andes reports a commercial RISC‑V product line from tiny MCUs to multi‑thousand‑core claims and says it shipped its first vector chip last year: the NX27B… | ||
| Safety + SBOMs + Zephyr RTOS | Kate Stewart | |
Safety + SBOMs + Zephyr RTOS - Kate Stewart, The Linux Foundation
Sensors and actuators are going to need to communicate reliably with the edge devices and up… | ||
| SERV: RISC-V for a Fistful of Gates | Olof Kindgren | 08m |
SERV claims the title of smallest RISC‑V CPU and keeps shrinking with recent optimizations, now ported to more than 30 FPGA boards and demonstrably taped out… | ||
| Getting Started with the Free ISS for the OpenHW CORE-V IP Roadmap | Kat Hsu | 11m |
Free Imperas RISC-V OVPsim Core-V provides a downloadable, Apache‑2.0 ISS that models CPU and memory for the OpenHW CORE-V family and is configurable for… | ||
| Towards a Comprehensive Open Source IoT RISC-V Stack | Frédéric Desbiens, Alexander Fedorov | 30m |
Claims a complete open-source IoT RISC-V stack made by combining OpenHW Group CORE‑V cores and Eclipse Foundation tooling, with concrete parts: CV32E2 / CV32 /… | ||
| Optimize Your Industrial IoT Application in Every Dimension | Shawn Prestridge | 22m |
Shows how to balance code size, execution speed, and energy on a RISC-V core using IAR tooling and standard C++ techniques, with concrete measurements of… | ||
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