RTLA Timerlat - the next step in scheduling latency analysis
summary
RTLA Timerlat is a combined kernel + userland tool that measures IRQ and thread latency split by doing most computation in-kernel to avoid excessive trace buffer writes and reduce overhead. It produces histograms, stops on thresholds (demo stopped at ~30 μs), and emits an auto-analysis with root-cause hints that attributes blocking to sources like Btrfs spinlocks or exit-from-idle. User-mode can run one thread per CPU, enable extra tracepoints, and the kernel pieces are already upstream for recent mainline kernels.
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chapters (20)
- 0:00RTLA Timerlat intro
- 3:51Why Timerlat was created
- 6:41Optimizing tracing with Timerlat
- 9:08Live demo: Timerlat top
- 11:20Auto analysis output
- 13:07Real-time theory behind Timerlat
- 14:31IRQ latency examples
- 17:43Thread latency in non-RT kernel
- 20:10OS noise trace points
- 23:46Advanced tracing with signals
- 26:17Histogram analysis insights
- 30:15User space workload integration
- 32:24Debugging with Timerlat
- 35:55Hardware latency detection
- 39:07RTLA future plans
- 42:17Q&A: locking analysis
- 44:01Kernel integration
- 46:33Benchmarking on mainline
- 47:37Production tracing libraries
- 49:43Q&A: user thread feature
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