Quick Cache DSR
summary
Implements a QUIC cache DSR where the front-end proxy writes QUIC headers and RPCs compact send instructions to a back-end cache that completes and sends encrypted QUIC packets directly to clients, avoiding double writes and state synchronization. Uses a unidirectional binary RPC with setup + send messages, pacing offload to reduce control chatter, and plans a 14-byte instruction encoding. Lab results show front-end CPU drops, back-end CPU rises, and normalized QPS improves; code runs in production small tests with observed CPU wins.
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chapters (12)
- 0:00Introduction
- 1:29Traditional CDN flow
- 2:12Design principles
- 3:16Front-end back-end flow
- 4:59Optimizing communication
- 6:28Packetization messages evolution
- 8:12Future packetization optimizations
- 9:18Transmission pacing
- 10:23Handling spurious loss
- 10:45Lab performance results
- 11:49Production state and CPU wins
- 12:12Future plans
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