A new Linux kernel subsystem for JESD204 RF Transceiver Systems
summary
A Linux kernel subsystem implements a finite state machine to coordinate up to dozens of JESD204 devices across clock trees and FPGA transceivers, automatically configuring lanes, frames and clocking and supporting JESD204C 32 Gbps rates. It brings up multi-chip setups (example: 4 RF transceivers and 14 devices) with deferred callbacks, rollbacks, per-device and per-link state ops, and diagnostics for lane errors and clock health. A Python configuration tool solves clock/VCO constraints and generates device trees; mainlining is planned and the framework already runs the example topology.
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chapters (20)
- 0:00Intro
- 0:56JESD204 Standard
- 2:22JESD204 Architecture
- 4:12Converter Device
- 4:43Logic Device
- 4:59Clock Generator
- 10:44Distributed Multichip Clock Synchronization
- 11:29Challenges of high-speed links
- 12:08JESD204 Interface Framework
- 12:58Scope & Requirements
- 15:26JESD204 FSM Linux Kernel Framework
- 20:22Design Principles (cont.)
- 23:05How does it work?
- 23:50The initialization data
- 25:06JESD204-FSM link states in a nutshell
- 28:394x ADRV9009 Example Block Diagram
- 29:25Kernel Boot Messages (devicetree parsing)
- 31:26Next Steps
- 31:42pyadi-jif: JESD Framework Configuration Tool
- 33:27References
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